The PC Board design is one of the most important ingredients in a successful testing strategy. Design for testability must be a priority during the beginning phases of a PC board design in order to ensure a high quality testing process when the assembly gets into production. Genesys Industries offers a Design for Testability review service to help you bridge the gap between design and production.

Design For Test Review including the following items:

• Review CAD data files to analyze node access issues. Generate a test probe report and testability report. Will make recommendations to improve access if needed.
• Review Electronic Schematics and make any necessary design change recommendations that will improve testing coverage.
• Will provide a general testing philosophy for the PCB assembly. Will provide specific testing solutions in circuitry where needed.
• Review customer supplied assembly drawings, dimensional drawings, bare or loaded PCB assemblies and will identify issues relating to test fixture construction.
• Review customer supplied testing requirements and generate a report of possible testing strategies including in-circuit and functional solutions.
• Generate Budgetary Quotation for Test Program and Test Fixture.

View and Download our Design for Testability Guidelines:

Download:
Genesys Design for Testability Guidelines (Acrobat format)
Genesys Design for Testability Guidelines (Microsoft Word format)
Keysight Essential Testability Guidelines for Current Technology (Acrobat format)

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Design for Testability Guidelines

1.0 Purpose

The purpose of this document is to describe the testability guidelines suggested when designing Printed Circuit Boards (PCB) and preparing CAD data files. These guidelines and rules will help ensure that a reliable in-circuit test fixture can be produced.

2.0 References

Keysight 3070 Family Users Manual
Keysight 3065 Family Users Manual

3.0 Test Probe Node Access

The design should provide 100% test probe access where possible for each net node (a minimum of 1 test target per net and multiple access for power nodes).

3.1 Power and Ground Node Access – the PC board layout must include adequate probing of power and ground nodes. Good power and ground connections are critical to the signal quality of powered tests.

3.1.1 Minimum ground Requirement – There must be a minimum of one ground test target per PC board tester power supply and one ground sense target (2 total). Example: if a PCB requires 3 power supply voltages, there must be a minimum of 4 ground test targets (3 voltages, 1 sense).

3.1.2 Other ground considerations – In addition to the minimum ground test target requirement, the amount of load current must be considered. The return current through ground is the sum of all of the individual power supply currents. The maximum current load per test target should not exceed 500mA. Example: If the sum currents of the power supplies is 5 amps, then 10 ground targets are required. The ground test targets should physically be evenly distributed if possible.

3.1.3 Minimum power supply requirement – There must be 3 test targets per power supply; 2 for power and 1 for power sense.

3.1.4 Power Supply current considerations – There should be one test target per 500 mA of power supply current load. These test targets should be evenly distributed on the PCB if possible.

3.1.5 Rules of Thumb – provide at least one power and ground test target for every 20 electrical nodes.

3.2 Digital Grounds – to help maintain good signal quality for high speed digital signals, test targets should be evenly distributed on the PCB with a digital ground test target for every 2.0″ square area.

3.3 Signal Node Access – there must be a minimum of 1 test probe location per net. However; it is preferable from an ATE standpoint to provide more than 1 probing location per net so that the automatic test generation software can attempt to optimize the distribution of test probes on the test fixture.

3.4 Node Access from One Side – significant effort must be made to allow all probing from the one side of the PCB. Use vias to bring all test targets to the one side of the board. If this is not possible, special fixturing can be incorporated to provide top or side access to test targets. These types of solutions add significant cost to the fixture, limit troubleshooting, and create test reliability issues.

3.5 Unused IC Leads – providing node access to unused IC leads is preferable but not required. Providing test access to unused pins reduces test development time and increases the test fault coverage as well as reducing manufacturing costs.

3.6 Etched edge connectors – should have a plated through hole for all component side connections as close to the edge connector as possible. The edge connector fingers will not normally be used for test probing.

3.7 Node Access Restrictions – in some cases adding node access would compromise the functionality of the design. In these cases other testing approaches should be incorporated such as: cluster testing a group of components, boundary scan, or functional testing. When these cases arise the designer should discuss testing methods with the test engineer as some design changes may be required to provide adequate test coverage.

4.0 Test Target Size and Spacing Tolerance Requirements

4.1 Test Target Types – several types of probing surfaces are possible. They are:

• Through-Hole Lead: this type of test target should have a known and consistent length.
• Test Pad: this is a solid flat surface ( .040″ diameter or square) without a through-hole.
• Test Via: is a plated through-hole with an exposed pad around it for probing. This type of via should have a hole diameter of .012″ +.000/-.003″ diameter.

4.2 Test Target Size – to provide reliable test probe contact to the PCB, a surface of .040″ for top side probing and .035″ for bottom side spacing is preferred.

• preferred: .040″
• acceptable: .035″
• extreme case: .025″

Test pad diameter less than .035″ require special fixturing: 50-mil probes, guided probe techniques, etc. and should be avoided.

4.3 Test Target Center to Center Spacing – 100-mil probes are the desired size used for vacuum test fixtures. The center spacing between test probes is:

• preferred 100-mil to 100-mil probe: 0.100″
• acceptable 100-mil to 100-mil probe: 0.085″
• 75-mil and 50-mil probes are available where the center to center spacing of 50mil to 50mil target can achieve a 0.060″ diameter dimension. However, 50-mil probes should be avoided.

4.4 Test Target Clearance – there must be a minimum .018″ annular ring around the edge of a test target that is free of components, exposed metal, other test targets, or obstructions. This clearance minimizes the risk of a test probe shorting to an adjacent component.

4.5 Tooling Holes to Test Targets Tolerance: +/- .002″

4.6 Test Target Surface – the surface to be probed must be solder coated or something conductively equivalent. Test vias should be filled with solder. This usually occurs automatically during the wave solder process.

Note: Test targets must not be covered by solder masks, silkscreens, or stick on labels.

4.7 Test Target Distribution – test targets should be as evenly distributed across the PCB as possible. The vacuum test fixture must overcome the counter force of the test probes. By evenly distributing the test probes, the PCB under test will remain as flat as possible during the vacuum process.

4.8 Panelized PCBs – a datum point must be provided for the individual board in a panel since the PCB is likely to be broken out and tested individually.

5.0 Tooling Pin Requirements All PCB’s must have tooling pin holes to provide orientation of the PCB to the test fixture. These holes should be placed near the opposing corners of the PCB and should not be plated. The edge of tooling holes should be no closer than 0.250 inches to the edge of the P.C. board on P.C. boards greater than 64 square inches and no closer than 0.100 inches on P.C. boards smaller than 64 square inches (where possible).

5.1 Number of tooling holes: minimum of 2 holes (usually on diagonal corners).

5.2 Tooling Hole Size:

• 0.125″ hole diameter preferred
• 0.090″ minimum hole diameter

5.3 Tooling Hole Tolerance: +0.003/-.000″ diameter

5.4 Tolerance between tooling holes: +/- .002″ diameter

5.5 Keep out area around hole: minimum .125″ area around the hole free from components and test targets. This is required for proper vacuum sealing.

5.6 Panelized PCBs: Tooling pin holes must be provided for the mother board and each of the individual boards.

6.0 Vacuum Fixture Sealing Issues

The board under test is held to the test fixture by vacuum. Any significant air leaks will cause intermittent or no operation. The following items cause air leaks and are difficult to seal without the proper design considerations.

6.1 PCB Edge – vacuum fixtures require an edge around the PCB for the purpose of mounting and sealing. This area should be free of components, holes, and test pads.
preferred: .250″
acceptable: .125″

6.2 Components on Probe Side of Board – components on the probing side of the PCB should not exceed .250″ in height. Components exceeding this height will require special fixture considerations such as cut-outs in the fixture plate. If a component height of greater than .250″ exists there must be a free area of .200″ around the component (example: no test pads closer than .200″).

6.3 Other design issues which present vacuum sealing challenges:
Drilled through spacers (Swaged).
Holes with Tyraps going through them.
Fasteners with the nut on the solder side.
Brackets which protrude below the board line.
Wires attached to the solder side or going through holes on the solder side.

When these or other issues can not be avoided, proper keep out areas (.200/.250″) must be incorporated to allow for proper sealing. 7.0 Maximum PCB Physical Dimension Requirements The physical size of a PCB should be restricted to the capability of equipment used to build and test the PCB. The requirements for the purpose of testing are:

• For Standard Fixtures: 14″ x 14″ (preferred)
• For Oversize Fixture: 14″ x 26″ (higher cost)

Note: these dimensions are for test fixtures only, they do not represent other types of manufacturing equipment such as wave solder, component locators, and others.

8.0 Electronic Testing Considerations:

An in-circuit testing approach is usually incorporated for testing PCBs; as such, some common design guidelines occur which can make the PCB easier to manufacture and test.

8.1 Disable bussed devices – A busable device must always have the capability of being disabled by the board tester in order to test other devices sharing the same bus. This of course is not just a test issue.

8.2 Disable upstream devices – Any device which drives other circuitry on a board that has the capability of being disabled should be designed such that the tester can disable it. This will relieve the device from the stress of being backdriven by the tester. Programmable devices, such as PALs, should incorporate a disabling capability if possible within the device.

8.3 Disable Free running clocks – Free running devices such as oscillators, crystals, or clock circuitry can prevent upstream devices from being tested adequately. These circuits must provide a disabling method. The preferable method is to electrically disable the circuit where possible; however, jumpers can be used in cases where this is not possible.

8.4 Use semiconductor device packages which provide disable pins – Several of the newer electronic devices provide packages which include a test pin or a group of test pins (example: intel 80386, motorola 68040). When asserted these devices can be tri-stated or placed in a known condition. These features should be included in the design when possible.

8.5 Custom or Programmable Devices – ATE tests for programmable devices are developed one of two ways: the first way is totally automatic using the appropriate device files, the second way is to manually code the test from the equations supplied. Tests for most of the commonly used PALs can be generated from the fuse map files. Other software packages exist which can provide an automatically created device test library. In either case the appropriate files must be supplied to generate the test code.

8.6 Use of Boundary Scan Parts – several devices are now available with boundary scan included (example: intel 80486 or motorola 68340). Often the BSDL code, which can be converted to test code automatically, is available from the manufacturer. Use of boundary scan will greatly reduce test development time as well as solve node access problems. Boundary scan does require some design effort but should be considered.

8.7 Devices with External Access Pins – Some micro’s have external access pins which determine whether code will be executed internal to the device or externally. This device pin should not be tied directly to a power or ground net. Most ATE device libraries for micro’s are coded for external access.

8.8 Digital Feedback Loops – during an in-circuit test digital devices are tested individually, where the device under test is isolated from the surrounding devices by a method known as backdriving. This form of testing usually isolates a failure down to the component level. It is difficult to isolate a device if an output of the device is directly or indirectly fed back into the input of the same device. For example: the clock output of a micro being fed into a ready input via a flip-flop. In cases like these pre-conditioning or disabling the device that feeds the input would remove the isolation problem.

8.9 Analog Feedback Loops – feedback conditions often occur in analog device circuits. Breaking up this circuitry may be helpful in isolating faults; however, this is not usually an issue since analog circuits are tested in a more functional approach.

Note: Remember, all of the above suggestions are meant to improve testability by reducing development time, troubleshooting time, and manufacturing costs. They however are not meant to hinder the functionality of the design.